Comparator architecture for reduced delay and lower static current

Described embodiments include a comparator circuit comprising an input voltage terminal, a reference voltage terminal, and a rising edge decode circuit having inputs coupled to the input voltage terminal and the reference voltage terminal. The rising edge output provides a rising edge decode signal indicating the input signal transitioned from being smaller than the reference voltage signal to being larger than the reference voltage signal. A falling edge decode circuit has inputs coupled to the input voltage terminal and the reference voltage terminal, and a falling edge output providing a falling edge decode signal indicating that the input signal transitioned from being larger than the reference voltage signal to being smaller than the reference voltage signal. Also, a decode logic circuit provides a comparator output in response to the rising edge decode signal and the falling edge decode signal.