Vertical memory cells

Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capa...

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Bibliographische Detailangaben
Hauptverfasser: Huang, Cheng-Ying, Morrow, Patrick, Mannebach, Ehren, Phan, Ahn, Rachmady, Willy, Dewey, Gilbert, Ma, Sean T, Lilak, Aaron, Sharma, Abhishek, Jun, Kimin, Yoo, Hui Jae
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.