Fail compare procedure

Methods, systems, and devices for a fail compare procedure are described. An apparatus may include a host device coupled with a memory device. An application specific integrated circuit (ASIC) associated with the host device (e.g., included in, coupled with) may include a set of comparators that output first bit information that includes respective states of at least two bits of data read from the memory device. The host device may compare (e.g., at the ASIC) the first bit information to second bit information that includes respective expected states of the at least two bits. Based on the comparison, the host device may determine whether a state of at least one bit of the first bit information is different than a state of a corresponding bit of the second bit information, and may output one or more signals including indications of a fail to a counter of the ASIC.