Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit

Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit

A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kim, Kyeong Min, Han, Yun Tack
Format: Patent
Sprache:eng
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Beschreibung
Zusammenfassung:A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.