Apparatus to synchronize clocks of configurable integrated circuit dies through an interconnect bridge

An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock s...

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Bibliographische Detailangaben
Hauptverfasser:	Nalamalpu, Ankireddy, Tang, Lai Guan, Subbareddy, Dheeraj
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.