Low power shared image pixel architecture

An image sensor may include a shared pixel circuit having multiple photodiodes coupled to a common floating diffusion node via respective charge transfer gates. First, the pixel circuit may be reset, and a sample-and-hold reset (SHR) value may be read out. Charge from a first of the photodiodes may be transferred to the floating diffusion node, and a first sample-and-hold signal (SHS) value may be read out. A first correlated double sampling (CDS) value is obtained by computing the difference between the SHR value and the first SHS value. Without resetting again, charge from a second of the photodiodes may be transferred to the floating diffusion node, and a second SHS value may be read out. A second CDS value is obtained by computing the difference between the first and second SHS values. Reading out the shared pixel circuit in this way substantially reduces power consumption.