Storage device that switches detector configuration sets between decoding iterations

A plurality of configuration sets are used with a detector coupled to a decoder. A processor is coupled to the memory registers and the detector and operable to load a first one of the configuration sets into the detector. The detector to attempts detection of the bits in the digital stream for a first iteration between the detector and the decoder using the first configuration set. After the first iteration, a second one of the configuration sets is loaded into the detector. The second configuration set is different than the first configuration set. The detector to attempts detection of the bits in the digital stream for a second iteration between the detector and the decoder using the second configuration set.