Methods and systems for translating virtual addresses in a virtual memory based system
An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; a Page Walk Cache (PWC) for storing page directory entries; and a memory controller configured to control accesses to the memo...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; a Page Walk Cache (PWC) for storing page directory entries; and a memory controller configured to control accesses to the memory devices. The processor in an embodiment is configured to send to the memory controller a page directory base and a plurality of memory offsets; and receive from the memory controller and store in the PWC at least one of the page directory entries. The memory controller is configured to: combine a first level page directory entry with a second level memory offset; read from memory a second page directory entry using the first level page directory entry and the second level memory offset; and send to the processor at least one of the page directory entries and a page table entry (PTE). |
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