Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip

A fault rules engine generates a plurality of fault rules files, each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design. Each fault rules file includes data quantifying a nominal delay for a given two-cycle test pattern and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects of a given cell type of the plurality of cell types in the IC design. An IC test engine extracts an input to output propagation delay for each cell instance from a standard delay format (SDF) file for the IC design and generates cell-aware test patterns for each cell instance of each cell type in the IC design based on the plurality of fault rules files and the extracted input to output propagation delays.