Memory controller and method performed by the memory controller

A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.