Method for adjusting reading speed of memory system, comparison circuit and memory system

The present disclosure relates to adjusting a reading speed of a memory system. A method for adjusting a reading speed of a memory system, including: generating an alternating sequence signal in which high levels and low levels appear alternately, associated with an output delay of the memory system; generating a reference signal having a predetermined frequency and a reference delay; generating a comparison result signal indicating a range of a difference between an output delay and the reference delay based on an alternating sequence signal and a reference signal; and determining whether a value indicated by a comparison result signal is a predetermined value, so as to adjust the reading speed of the memory system based on a determination result.