Capacitive voltage dividers coupled to voltage regulators

A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method include...

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Bibliographische Detailangaben
1. Verfasser:	Rowley, Matthew D
Format:	Patent
Sprache:	eng
Schlagworte:	APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS CALCULATING COMPUTING CONTROL OR REGULATION THEREOF CONTROLLING CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY GENERATION INFORMATION STORAGE PHYSICS REGULATING STATIC STORES SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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Beschreibung
Zusammenfassung:	A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method includes determining whether the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate. The method further includes selectably coupling, responsive to a determination of the low power mode, the CVD and the LVR and sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, where the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.