Package for a multi-chip power semiconductor device

A package includes: a package body having an outside housing including first and second package sides and package sidewalls that extend between the first and second package sides; first and second electrically conductive interface layers spaced apart from each other at the outside housing; and first and second power semiconductor chips arranged within the package body, both chips having a respective first load terminal and a respective second load terminal. The first load terminals are electrically connected to each other within the package body. The second load terminal of the first chip is electrically connected to the first electrically conductive interface layer. The second load terminal of the second chip is electrically connected to the second electrically conductive interface layer. The outside housing of the package body further includes a creepage structure having a minimum dimension between the first electrically conductive interface layer and the second electrically conductive interface layer.