Timing-aware testing

Timing-aware testing

In order to expedite testing (such as silicon chip testing), a test pattern that indicates a timing, order, and frequency (e.g., speed) of signals sent during the test may be divided into different portions. Also, a frequency at which each portion of the test pattern is to be run is determined. Each...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Lee, Shang-Ju, Ko, Li-Wei, Lin, Shyh-Horng, Da Silva, Francisco M
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:In order to expedite testing (such as silicon chip testing), a test pattern that indicates a timing, order, and frequency (e.g., speed) of signals sent during the test may be divided into different portions. Also, a frequency at which each portion of the test pattern is to be run is determined. Each portion is run at a frequency that can be supported by only that portion. As a result, the slowest portion of the test pattern only limits the frequency at which its portion is run, while other portions are run at a faster frequency. This reduces a time taken to run the test pattern in a testing environment.