Multiple dies hardware processors and methods
Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another...
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creator | Singh, Tejpal Chamberlain, Jeffrey D Sistla, Krishnakanth V Kumashikar, Mahesh K Geetha, Vedaraman Ayers, John R Pasdast, Gerald Nassif, Nevine Eachempati, Siva Soumya Nimmagadda, Srikanth Halleck, William R Subbareddy, Dheeraj R Liu, Yen-Cheng Varma, Ankush Chrysos, George Z Molnar, Carleton L |
description | Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11294852B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11294852B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11294852B23</originalsourceid><addsrcrecordid>eNrjZND1Lc0pySzISVVIyUwtVshILEopTyxKVSgoyk9OLS7OLypWSMxLUchNLcnITynmYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGhkaWJhamRk5GxsSoAQDqeiqh</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Multiple dies hardware processors and methods</title><source>esp@cenet</source><creator>Singh, Tejpal ; Chamberlain, Jeffrey D ; Sistla, Krishnakanth V ; Kumashikar, Mahesh K ; Geetha, Vedaraman ; Ayers, John R ; Pasdast, Gerald ; Nassif, Nevine ; Eachempati, Siva Soumya ; Nimmagadda, Srikanth ; Halleck, William R ; Subbareddy, Dheeraj R ; Liu, Yen-Cheng ; Varma, Ankush ; Chrysos, George Z ; Molnar, Carleton L</creator><creatorcontrib>Singh, Tejpal ; Chamberlain, Jeffrey D ; Sistla, Krishnakanth V ; Kumashikar, Mahesh K ; Geetha, Vedaraman ; Ayers, John R ; Pasdast, Gerald ; Nassif, Nevine ; Eachempati, Siva Soumya ; Nimmagadda, Srikanth ; Halleck, William R ; Subbareddy, Dheeraj R ; Liu, Yen-Cheng ; Varma, Ankush ; Chrysos, George Z ; Molnar, Carleton L</creatorcontrib><description>Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220405&DB=EPODOC&CC=US&NR=11294852B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220405&DB=EPODOC&CC=US&NR=11294852B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Singh, Tejpal</creatorcontrib><creatorcontrib>Chamberlain, Jeffrey D</creatorcontrib><creatorcontrib>Sistla, Krishnakanth V</creatorcontrib><creatorcontrib>Kumashikar, Mahesh K</creatorcontrib><creatorcontrib>Geetha, Vedaraman</creatorcontrib><creatorcontrib>Ayers, John R</creatorcontrib><creatorcontrib>Pasdast, Gerald</creatorcontrib><creatorcontrib>Nassif, Nevine</creatorcontrib><creatorcontrib>Eachempati, Siva Soumya</creatorcontrib><creatorcontrib>Nimmagadda, Srikanth</creatorcontrib><creatorcontrib>Halleck, William R</creatorcontrib><creatorcontrib>Subbareddy, Dheeraj R</creatorcontrib><creatorcontrib>Liu, Yen-Cheng</creatorcontrib><creatorcontrib>Varma, Ankush</creatorcontrib><creatorcontrib>Chrysos, George Z</creatorcontrib><creatorcontrib>Molnar, Carleton L</creatorcontrib><title>Multiple dies hardware processors and methods</title><description>Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND1Lc0pySzISVVIyUwtVshILEopTyxKVSgoyk9OLS7OLypWSMxLUchNLcnITynmYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGhkaWJhamRk5GxsSoAQDqeiqh</recordid><startdate>20220405</startdate><enddate>20220405</enddate><creator>Singh, Tejpal</creator><creator>Chamberlain, Jeffrey D</creator><creator>Sistla, Krishnakanth V</creator><creator>Kumashikar, Mahesh K</creator><creator>Geetha, Vedaraman</creator><creator>Ayers, John R</creator><creator>Pasdast, Gerald</creator><creator>Nassif, Nevine</creator><creator>Eachempati, Siva Soumya</creator><creator>Nimmagadda, Srikanth</creator><creator>Halleck, William R</creator><creator>Subbareddy, Dheeraj R</creator><creator>Liu, Yen-Cheng</creator><creator>Varma, Ankush</creator><creator>Chrysos, George Z</creator><creator>Molnar, Carleton L</creator><scope>EVB</scope></search><sort><creationdate>20220405</creationdate><title>Multiple dies hardware processors and methods</title><author>Singh, Tejpal ; Chamberlain, Jeffrey D ; Sistla, Krishnakanth V ; Kumashikar, Mahesh K ; Geetha, Vedaraman ; Ayers, John R ; Pasdast, Gerald ; Nassif, Nevine ; Eachempati, Siva Soumya ; Nimmagadda, Srikanth ; Halleck, William R ; Subbareddy, Dheeraj R ; Liu, Yen-Cheng ; Varma, Ankush ; Chrysos, George Z ; Molnar, Carleton L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11294852B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Singh, Tejpal</creatorcontrib><creatorcontrib>Chamberlain, Jeffrey D</creatorcontrib><creatorcontrib>Sistla, Krishnakanth V</creatorcontrib><creatorcontrib>Kumashikar, Mahesh K</creatorcontrib><creatorcontrib>Geetha, Vedaraman</creatorcontrib><creatorcontrib>Ayers, John R</creatorcontrib><creatorcontrib>Pasdast, Gerald</creatorcontrib><creatorcontrib>Nassif, Nevine</creatorcontrib><creatorcontrib>Eachempati, Siva Soumya</creatorcontrib><creatorcontrib>Nimmagadda, Srikanth</creatorcontrib><creatorcontrib>Halleck, William R</creatorcontrib><creatorcontrib>Subbareddy, Dheeraj R</creatorcontrib><creatorcontrib>Liu, Yen-Cheng</creatorcontrib><creatorcontrib>Varma, Ankush</creatorcontrib><creatorcontrib>Chrysos, George Z</creatorcontrib><creatorcontrib>Molnar, Carleton L</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Singh, Tejpal</au><au>Chamberlain, Jeffrey D</au><au>Sistla, Krishnakanth V</au><au>Kumashikar, Mahesh K</au><au>Geetha, Vedaraman</au><au>Ayers, John R</au><au>Pasdast, Gerald</au><au>Nassif, Nevine</au><au>Eachempati, Siva Soumya</au><au>Nimmagadda, Srikanth</au><au>Halleck, William R</au><au>Subbareddy, Dheeraj R</au><au>Liu, Yen-Cheng</au><au>Varma, Ankush</au><au>Chrysos, George Z</au><au>Molnar, Carleton L</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Multiple dies hardware processors and methods</title><date>2022-04-05</date><risdate>2022</risdate><abstract>Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Multiple dies hardware processors and methods |
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