Static address allocation by passive electronics

Static address allocation by passive electronics

A bus node IC comprises at least one static address selection terminal and a detecting circuit for detecting a state of the static address selection terminal, and a communication circuit adapted for determining a node address identifier taking the detected state into account. The detecting circuit i...

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1. Verfasser: Vandersteegen, Peter
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator Vandersteegen, Peter
description A bus node IC comprises at least one static address selection terminal and a detecting circuit for detecting a state of the static address selection terminal, and a communication circuit adapted for determining a node address identifier taking the detected state into account. The detecting circuit is adapted for detecting the state by determining an electrical property of a passive electronic component when connected to the static address selection terminal. The communication circuit is adapted for receiving/transmitting data over the data bus in accordance with a first communication protocol using the node address identifier for identification of the IC, and for receiving/transmitting data over said data bus in accordance with a second communication protocol using a further node address identifier for identification of the IC, wherein the communication circuit is adapted for configuring the further node address identifier by using data received using the first protocol.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11281614B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11281614B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11281614B23</originalsourceid><addsrcrecordid>eNrjZDAILkksyUxWSExJKUotLlZIzMnJTwaK5OcpJFUqFCQWF2eWpSqk5qQmlxTl52UmF_MwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUkvjQYENDIwtDM0MTJyNjYtQAAIQAK8A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Static address allocation by passive electronics</title><source>esp@cenet</source><creator>Vandersteegen, Peter</creator><creatorcontrib>Vandersteegen, Peter</creatorcontrib><description>A bus node IC comprises at least one static address selection terminal and a detecting circuit for detecting a state of the static address selection terminal, and a communication circuit adapted for determining a node address identifier taking the detected state into account. The detecting circuit is adapted for detecting the state by determining an electrical property of a passive electronic component when connected to the static address selection terminal. The communication circuit is adapted for receiving/transmitting data over the data bus in accordance with a first communication protocol using the node address identifier for identification of the IC, and for receiving/transmitting data over said data bus in accordance with a second communication protocol using a further node address identifier for identification of the IC, wherein the communication circuit is adapted for configuring the further node address identifier by using data received using the first protocol.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220322&amp;DB=EPODOC&amp;CC=US&amp;NR=11281614B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220322&amp;DB=EPODOC&amp;CC=US&amp;NR=11281614B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Vandersteegen, Peter</creatorcontrib><title>Static address allocation by passive electronics</title><description>A bus node IC comprises at least one static address selection terminal and a detecting circuit for detecting a state of the static address selection terminal, and a communication circuit adapted for determining a node address identifier taking the detected state into account. The detecting circuit is adapted for detecting the state by determining an electrical property of a passive electronic component when connected to the static address selection terminal. The communication circuit is adapted for receiving/transmitting data over the data bus in accordance with a first communication protocol using the node address identifier for identification of the IC, and for receiving/transmitting data over said data bus in accordance with a second communication protocol using a further node address identifier for identification of the IC, wherein the communication circuit is adapted for configuring the further node address identifier by using data received using the first protocol.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAILkksyUxWSExJKUotLlZIzMnJTwaK5OcpJFUqFCQWF2eWpSqk5qQmlxTl52UmF_MwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUkvjQYENDIwtDM0MTJyNjYtQAAIQAK8A</recordid><startdate>20220322</startdate><enddate>20220322</enddate><creator>Vandersteegen, Peter</creator><scope>EVB</scope></search><sort><creationdate>20220322</creationdate><title>Static address allocation by passive electronics</title><author>Vandersteegen, Peter</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11281614B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>Vandersteegen, Peter</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vandersteegen, Peter</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Static address allocation by passive electronics</title><date>2022-03-22</date><risdate>2022</risdate><abstract>A bus node IC comprises at least one static address selection terminal and a detecting circuit for detecting a state of the static address selection terminal, and a communication circuit adapted for determining a node address identifier taking the detected state into account. The detecting circuit is adapted for detecting the state by determining an electrical property of a passive electronic component when connected to the static address selection terminal. The communication circuit is adapted for receiving/transmitting data over the data bus in accordance with a first communication protocol using the node address identifier for identification of the IC, and for receiving/transmitting data over said data bus in accordance with a second communication protocol using a further node address identifier for identification of the IC, wherein the communication circuit is adapted for configuring the further node address identifier by using data received using the first protocol.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Static address allocation by passive electronics
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T20%3A03%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Vandersteegen,%20Peter&rft.date=2022-03-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11281614B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true