Static address allocation by passive electronics
A bus node IC comprises at least one static address selection terminal and a detecting circuit for detecting a state of the static address selection terminal, and a communication circuit adapted for determining a node address identifier taking the detected state into account. The detecting circuit i...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A bus node IC comprises at least one static address selection terminal and a detecting circuit for detecting a state of the static address selection terminal, and a communication circuit adapted for determining a node address identifier taking the detected state into account. The detecting circuit is adapted for detecting the state by determining an electrical property of a passive electronic component when connected to the static address selection terminal. The communication circuit is adapted for receiving/transmitting data over the data bus in accordance with a first communication protocol using the node address identifier for identification of the IC, and for receiving/transmitting data over said data bus in accordance with a second communication protocol using a further node address identifier for identification of the IC, wherein the communication circuit is adapted for configuring the further node address identifier by using data received using the first protocol. |
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