Spurious components reduction

An integrated circuit includes a first input port configured to receive a supply voltage from a switched-mode power supply (SMPS), where frequency components of the supply voltage include harmonics of a reference frequency, where the reference frequency is equal to a first frequency divided by a factor; and a spurious components cancellation circuit coupled to the first input port, where the spurious components cancellation circuit is configured to: generate a first clock signal having the reference frequency; adjust an amplitude and a phase of the first clock signal to form a compensation signal; and add the compensation signal to the supply voltage to produce a modified supply voltage with reduced frequency components at one or more harmonic frequencies of the reference frequency.