Processor to JTAG test data register interface

A method includes disconnecting a data bus connecting a test access port (TAP) controller of an integrated circuit (IC) chip to a plurality of test data registers deployed on the chip, simultaneously supplying test data to multiple test data registers among the plurality of test data registers, and...

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Bibliographische Detailangaben
Hauptverfasser:	Lee, Abby Huggins, Fan, Chuanyun, Zhang, Fanchen, Tu, Jing, Karabinas, Thomas, Seetharaman, Venkatasubramanian
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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Beschreibung
Zusammenfassung:	A method includes disconnecting a data bus connecting a test access port (TAP) controller of an integrated circuit (IC) chip to a plurality of test data registers deployed on the chip, simultaneously supplying test data to multiple test data registers among the plurality of test data registers, and storing test response data, received from the plurality of test data registers and responsive to the test data, in storage registers deployed on the chip.