Scalable matrix node engine with configurable data formats

A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes one or more processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction specif...

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Bibliographische Detailangaben
Hauptverfasser: Das Sarma, Debjit, McGee, William, Talpes, Emil
Format: Patent
Sprache:eng
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Zusammenfassung:A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes one or more processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias.