Compute optimization mechanism for deep neural networks

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memo...

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Hauptverfasser:	Satish, Nadathur Rajagopalan, Ashbaugh, Ben J, Galoppo Von Borries, Nicolas C, Akhbari, Farshad, Ray, Joydeep, Srinivasa, Narayan, Maiyuran, Subramaniam, Schluessler, Travis T, Feit, John H, Gottschlich, Justin E, Boles, Jeffery S, Vaidyanathan, Karthik, Surti, Prasoonkumar, Nurvitadhi, Eriko, Burke, Devan, Hurd, Linda L, Appu, Abhishek R, Chen, Feng, Baghsorkhi, Sara S, Lake, Adam T, Lin, Tsung-Han, Fu, Wenyin, Koker, Altug, Kim, Dukhwan, Sinha, Kamal, Vembu, Balaji, Barik, Rajkishore, Mastronarde, Josh B
Format:	Patent
Sprache:	eng
Schlagworte:	ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING CRYPTOGRAPHY DISPLAY EDUCATION ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS SEALS
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Beschreibung
Zusammenfassung:	An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.