Apparatuses, systems, and methods for address scrambling in a volatile memory device

Apparatuses, systems, and methods for address scrambling in a volatile memory device

A volatile memories includes an address scrambler configured to scramble at least a portion of a received addresses to obscure address topography of a memory array using at least one scramble key. The at least one scramble key is generated by a random number generator. The address scrambler is confi...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Morgan, Donald M, Ayyapureddi, Sujeet
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A volatile memories includes an address scrambler configured to scramble at least a portion of a received addresses to obscure address topography of a memory array using at least one scramble key. The at least one scramble key is generated by a random number generator. The address scrambler is configured to perform logical bitwise operations using between a received address and the at least one scramble key to generate the scrambled row address.