Timing synchronization for clock systems with asymmetric path delay

Techniques are disclosed for performing time synchronization for a plurality of computing devices that exhibit asymmetric path delay. In one example, processing circuitry receives data indicative of a graph comprising a plurality of nodes and vertices, wherein each node represents a clock and each v...

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Bibliographische Detailangaben

Hauptverfasser:	Li, Danjue, Wang, Lanfa
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY MULTIPLEX COMMUNICATION WIRELESS COMMUNICATIONS NETWORKS
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