Timing synchronization for clock systems with asymmetric path delay

Techniques are disclosed for performing time synchronization for a plurality of computing devices that exhibit asymmetric path delay. In one example, processing circuitry receives data indicative of a graph comprising a plurality of nodes and vertices, wherein each node represents a clock and each vertex represents a bidirectional path between two clocks. Each bidirectional path has a first path delay in a first direction that is different from a second path delay in a second direction. The processing circuitry determines one or more closed loops in the graph and a path delay of the closed loop. The processing circuitry applies a minimization function to the path delay of each closed loop to determine values for the first and second path delays of each bidirectional path. The processing circuitry applies, based on the values for the first and second path delays of each bidirectional path, a time correction to a clock.