Optimizing gate profile for performance and gate fill

Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite...

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Bibliographische Detailangaben
Hauptverfasser:	Rahhal-Orabi, Nadia M, Ghani, Tahir, Metz, Matthew V, Rachmady, Willy, Dewey, Gilbert, Kavalieros, Jack T, Mohapatra, Chandra S, Murthy, Anand S
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fin.