Pixel charge control circuit in digital devices for images acquisition

A digital device for image acquisition (10) comprises at least one selection decoder circuit (60) and a plurality of sub-blocks (50) each comprising one or more pixels (20) and a corresponding charge control circuit (30) which provides a circuit suitable for realizing a logic port of the AND type (31) having a selector input terminal (34) which receives the selection signal from the selection decoder circuit (60) and a suitable enabling input terminal (35) to receive an enabling signal; and interruption organs (32) connected to the reset terminal (21) of the pixel (20) to transmit a reset signal constituted alternatively by a signal output from the aforesaid circuit suitable for realizing a logic port of the AND type (31) or from a global reset signal transmitted to a corresponding global reset terminal (38). The reset signal of a sub-block can be controlled directly by the selection decoder (60), while the global signal transmitted to the global reset terminal (38) may be a digital signal suitable for performing a global reset of all the pixels of the device; it can be an analog global signal of the type suitable to limit the blooming effect or to obtain high dynamics.