Gate-lifted NMOS ESD protection device
An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to r...
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| creator | Lai, Da-Wei Peters, Wilhelmus Cornelis Maria Sque, Stephen John |
| description | An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad. |
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CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS ; GENERATION ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210928&DB=EPODOC&CC=US&NR=11133299B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210928&DB=EPODOC&CC=US&NR=11133299B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lai, Da-Wei</creatorcontrib><creatorcontrib>Peters, Wilhelmus Cornelis Maria</creatorcontrib><creatorcontrib>Sque, Stephen John</creatorcontrib><title>Gate-lifted NMOS ESD protection device</title><description>An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</subject><subject>GENERATION</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBzTyxJ1c3JTCtJTVHw8_UPVnANdlEoKMovSU0uyczPU0hJLctMTuVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGhsbGRpaWTkbGxKgBAAA4JrE</recordid><startdate>20210928</startdate><enddate>20210928</enddate><creator>Lai, Da-Wei</creator><creator>Peters, Wilhelmus Cornelis Maria</creator><creator>Sque, Stephen John</creator><scope>EVB</scope></search><sort><creationdate>20210928</creationdate><title>Gate-lifted NMOS ESD protection device</title><author>Lai, Da-Wei ; Peters, Wilhelmus Cornelis Maria ; Sque, Stephen John</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11133299B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</topic><topic>GENERATION</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lai, Da-Wei</creatorcontrib><creatorcontrib>Peters, Wilhelmus Cornelis Maria</creatorcontrib><creatorcontrib>Sque, Stephen John</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lai, Da-Wei</au><au>Peters, Wilhelmus Cornelis Maria</au><au>Sque, Stephen John</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Gate-lifted NMOS ESD protection device</title><date>2021-09-28</date><risdate>2021</risdate><abstract>An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION SEMICONDUCTOR DEVICES |
| title | Gate-lifted NMOS ESD protection device |
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