Sparse optimizations for a matrix accelerator architecture

Sparse optimizations for a matrix accelerator architecture

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embod...

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Hauptverfasser: Ould-Ahmed-Vall, Elmoustapha, Macpherson, Mike, Kim, SungYe, George, Varghese, Ranganathan, Vasanth, Surti, Prasoonkumar, Valentin, Andrei, Striramassarma, Lakshminarayanan, Vemulapalli, Vikranth, Koker, Altug, Hunter, Jr., Arthur, Ray, Joydeep, Sadler, William, Maiyuran, Subramaniam, Appu, Abhishek, Janus, Scott, Garg, Ashutosh, Harel, Yoav
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Beschreibung
Zusammenfassung:Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.