Instruction generation for validation of processor functionality

Examples of instruction generation for validation of processor functionality are described. In an example, a validation instruction to be inserted in an instruction stream is selected. The validation instruction being generated based on an instruction set architecture of a processor-under-test (PUT). It is identified whether a hardware register of the PUT, is available for storing an outcome of execution of the validation instruction by the PUT. The validation instruction is inserted in the instruction stream, in response to identifying that the hardware register is available for storing the outcome. A set of data backup instructions is inserted in the instruction stream, in response to identifying that the hardware register is unavailable for storing the outcome. The set of data backup instructions is to store respective register values of each of the plurality of hardware registers in a primary memory.