Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection

Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.