Integrated arrangements of pull-up transistors and pull-down transistors, and integrated static memory

Integrated arrangements of pull-up transistors and pull-down transistors, and integrated static memory

Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: Bell, Debra M
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Beschreibung
Zusammenfassung:Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level.