Main-auxiliary field-effect transistor configurations with an auxiliary stack and interior parallel transistors
Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that in...
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| creator | Fuh, Hanching Whitefield, David Scott Bartle, Dylan Charles Wang, Hailing DiCarlo, Paul T Mason, Jerod F |
| description | Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs. |
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| subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PULSE TECHNIQUE SEMICONDUCTOR DEVICES TRANSMISSION |
| title | Main-auxiliary field-effect transistor configurations with an auxiliary stack and interior parallel transistors |
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