System and method for providing a configurable timing control for a memory system

A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output data from the flip-flops via the multiplexer with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.