Semiconductor memory device for executing a read operation at high speed

According to one embodiment, a semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.