Dummy MOL removal for performance enhancement

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plur...

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Bibliographische Detailangaben
Hauptverfasser:	Yang, Hui-Ting, Chen, Chun-Kuang, Shen, Meng-Hung, Sio, Kam-Tou, Chen, Chih-Liang, Lai, Chih-Ming, Tzeng, Jiann-Tyng, Liu, Ru-Gun, Lin, Wei-Cheng, Young, Charles Chew-Yuen
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.