Apparatus and method for ternary logic synthesis with modified Quine-McCluskey algorithm

Apparatus and method for ternary logic synthesis with modified Quine-McCluskey algorithm

Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kang, Seokhyeong, Lee, Sung-Yun, Kim, Sunmean
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.