Start-and-stop detecting apparatus and method for I3C bus

A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.