Semiconductor memory device
A semiconductor memory device includes a cache latch group including a plurality of even latch stages and a plurality of odd latch stages arranged alternately with each other; and a sense amplifier group coupled to the cache latch group through a plurality of first bit out lines respectively corresp...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A semiconductor memory device includes a cache latch group including a plurality of even latch stages and a plurality of odd latch stages arranged alternately with each other; and a sense amplifier group coupled to the cache latch group through a plurality of first bit out lines respectively corresponding to the plurality of even latch stages and through a plurality of second bit out lines respectively corresponding to the plurality of odd latch stages. |
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