Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier

Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier

A leadless package includes an at least partially electrically conductive carrier having a mounting section and a lead section, an electronic chip mounted on the mounting section, and an encapsulant at least partially encapsulating the electronic chip and partially encapsulating the carrier so that...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Liebl, Christoph, Tay, Bun Kian, Bemmerl, Thomas, Chan, Kuok Wai, Tay, Wee Boon, Yong, Wae Chet
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A leadless package includes an at least partially electrically conductive carrier having a mounting section and a lead section, an electronic chip mounted on the mounting section, and an encapsulant at least partially encapsulating the electronic chip and partially encapsulating the carrier so that at least part of an interior sidewall of the lead section not forming part of an exterior sidewall of the package is exposed.