Test circuit and semiconductor device

A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.