Parallel implementation of a dithering algorithm for high data rate display devices

A display device includes a display controller that performs a high-throughput dithering operation. The display controller performs a quantization operation with pixel values generated by a graphics processor to generate quantized pixel values and residual error values. The display controller distributes the residual error values associated with a first group of quantized pixel values to a second group of quantized pixel values based on a set of distribution weights. A given distribution weight defines what fraction of a given residual error value is distributed to a given quantized pixel value included in the second group of quantized pixel values. The distribution weights are calibrated to permit the display controller to compute different fractions of residual error values using bit shifting logic instead of complex combinatorial logic.