Semiconductor arrangement having a circuit board with a patterned metallization layer

A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks, and individual semiconductor chips each having a controllable semiconductor element, first and second load electrodes, and a control electrode. The first conductor track has a base section and further sections extending from the base section. The second conductor track has sections. The further sections of the first conductor track and the sections of the second conductor track extend parallel to one another in a first direction at least over a same lateral dimension of the individual semiconductor chips. The further sections of the first conductor track alternate with the sections of the second conductor track in a second direction orthogonal to the first direction. The individual semiconductor chips are arranged on the sections of the second conductor track. The first load electrodes are connected to the further sections of the first conductor track.