Low-power fast-setting delay circuit

In certain aspects, a delay circuit includes a delay line including a bias input. The delay circuit also includes a bias generator including a clock input, and a bias output, wherein the bias output of the bias generator is coupled to the bias input of the delay line. The delay circuit further inclu...

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Bibliographische Detailangaben
Hauptverfasser:	Shing, George, Fertsch, Michael
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PULSE TECHNIQUE TRANSMISSION
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	In certain aspects, a delay circuit includes a delay line including a bias input. The delay circuit also includes a bias generator including a clock input, and a bias output, wherein the bias output of the bias generator is coupled to the bias input of the delay line. The delay circuit further includes a multiplexer including a first input, a second input, and an output, wherein the first input of the multiplexer is configured to receive a first clock signal, the second input of the multiplexer is configured to receive a second clock signal, and the output of the multiplexer is coupled to the clock input of the bias generator.