Method of manufacturing semiconductor device comprising doped gate spacer
A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall...
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| creator | Chan, Chia-Ling Lin, Mu-Tsang Cheng, Tung-Wen Lo, Wei-Yang |
| description | A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10879399B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10879399B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10879399B23</originalsourceid><addsrcrecordid>eNqNyk0OQTEUhuFODAR7OBYgwR3QKSEMjDC-aU6_Xk20p-mP9QuxAKN38D5jdb6gPsSSOAomNme4tuzjQAXBs0TbuEomi5dnEEtI2ZfPt5JgaTAVVJJh5KkaOfMsmP06UfPj4bY_LZCkx9dE1P5-XS23G91pvVt3_5g3Lp41fw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of manufacturing semiconductor device comprising doped gate spacer</title><source>esp@cenet</source><creator>Chan, Chia-Ling ; Lin, Mu-Tsang ; Cheng, Tung-Wen ; Lo, Wei-Yang</creator><creatorcontrib>Chan, Chia-Ling ; Lin, Mu-Tsang ; Cheng, Tung-Wen ; Lo, Wei-Yang</creatorcontrib><description>A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201229&DB=EPODOC&CC=US&NR=10879399B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201229&DB=EPODOC&CC=US&NR=10879399B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chan, Chia-Ling</creatorcontrib><creatorcontrib>Lin, Mu-Tsang</creatorcontrib><creatorcontrib>Cheng, Tung-Wen</creatorcontrib><creatorcontrib>Lo, Wei-Yang</creatorcontrib><title>Method of manufacturing semiconductor device comprising doped gate spacer</title><description>A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyk0OQTEUhuFODAR7OBYgwR3QKSEMjDC-aU6_Xk20p-mP9QuxAKN38D5jdb6gPsSSOAomNme4tuzjQAXBs0TbuEomi5dnEEtI2ZfPt5JgaTAVVJJh5KkaOfMsmP06UfPj4bY_LZCkx9dE1P5-XS23G91pvVt3_5g3Lp41fw</recordid><startdate>20201229</startdate><enddate>20201229</enddate><creator>Chan, Chia-Ling</creator><creator>Lin, Mu-Tsang</creator><creator>Cheng, Tung-Wen</creator><creator>Lo, Wei-Yang</creator><scope>EVB</scope></search><sort><creationdate>20201229</creationdate><title>Method of manufacturing semiconductor device comprising doped gate spacer</title><author>Chan, Chia-Ling ; Lin, Mu-Tsang ; Cheng, Tung-Wen ; Lo, Wei-Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10879399B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chan, Chia-Ling</creatorcontrib><creatorcontrib>Lin, Mu-Tsang</creatorcontrib><creatorcontrib>Cheng, Tung-Wen</creatorcontrib><creatorcontrib>Lo, Wei-Yang</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chan, Chia-Ling</au><au>Lin, Mu-Tsang</au><au>Cheng, Tung-Wen</au><au>Lo, Wei-Yang</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of manufacturing semiconductor device comprising doped gate spacer</title><date>2020-12-29</date><risdate>2020</risdate><abstract>A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method of manufacturing semiconductor device comprising doped gate spacer |
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