Vector atomic memory update instruction

Processing circuitry (85) supports a vector atomic memory update instruction identifying an address vector, for triggering at least one atomic memory update operation for performing an atomic memory update to a memory location having an address determined based on a corresponding active data element...

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Bibliographische Detailangaben
1. Verfasser: Stephens, Nigel John
Format: Patent
Sprache:eng
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Zusammenfassung:Processing circuitry (85) supports a vector atomic memory update instruction identifying an address vector, for triggering at least one atomic memory update operation for performing an atomic memory update to a memory location having an address determined based on a corresponding active data element of the address vector. When a fault condition is determined for the address determined using a given faulting active data element of the address vector, atomic memory update operations for that element and any subsequent element in a predetermined sequence are suppressed. If the faulting element is the first active data element in the sequence, a fault handling response is triggered, while otherwise the fault handling response is suppressed and status information is stored indicating which element is the faulting element.