Transistor arrangement with a load transistor and a sense transistor

A transistor arrangement and a method are disclosed. The transistor arrangement includes: a drift and drain region arranged in a semiconductor body and connected to a drain node; a plurality of load transistor cells each including a source region integrated in a first region of the semiconductor body; a plurality of sense transistor cells each including a source region integrated in a second region of the semiconductor body; a first source node electrically connected to the source region of each load transistor cell via a first source conductor having a first area specific resistance; and a second source node electrically connected to the source region of each sense transistor cell via a second source conductor having a second area specific resistance. The area specific resistance of the second source conductor is greater than the area specific resistance of the first source conductor.