Adaptive power down of intra-chip interconnect

Adaptive power down of intra-chip interconnect

An integrated circuit comprising a plurality of last-level caches, a plurality of processor cores configured to access data in the plurality of last-level caches, and an interconnect network. The plurality of last-level caches can be placed in at least a high cache-power consumption mode and a low c...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Shearer, Robert Allen, Lai, Patrick P
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:An integrated circuit comprising a plurality of last-level caches, a plurality of processor cores configured to access data in the plurality of last-level caches, and an interconnect network. The plurality of last-level caches can be placed in at least a high cache-power consumption mode and a low cache-power consumption mode. The plurality of last-level caches includes a first last-level cache and a second last-level cache. The interconnect network comprises a plurality of links that can be placed in at least a high link-power consumption mode and a low link-power consumption mode. The interconnect network is configured to cause a first subset of the plurality of links to be placed in the low link-power consumption mode based at least in part on the first last-level cache being in the low cache-power consumption mode.