Resistive memory devices

A resistive memory device includes a memory cell array including a memory cell connected between a first signal line and a second signal line, an instance of control circuitry configured to generate a write control signal to control a data writing operation performed on the memory cell and a read control signal to control a data reading operation of reading data stored in the memory cell, a write circuit configured to supply a write current to support the data writing operation, a read circuit configured to supply a read current to support the data reading operation, a column decoder circuit configured to electrically connect the write circuit to the first signal line, based on the write control signal; and a row decoder circuit configured to electrically connect the read circuit to the second signal line, based on the read control signal.