Display apparatus and inter-chip bus thereof

Display apparatus and inter-chip bus thereof

A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Huang, Chih-Chuan, Yu, Shang-Han, Chen, Sung-Bo
Format: Patent
Sprache:eng
Schlagworte:
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CALCULATING
COMPUTING
COUNTING
CRYPTOGRAPHY
DISPLAY
EDUCATION
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
SEALS
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Beschreibung
Zusammenfassung:A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area. The N slave TEDs are disposed corresponding to a second display area˜a (N+1)-th display area respectively and controlled by the master TED. The inter-chip bus includes a first wire and a second wire coupled between the master TED and N slave TEDs respectively and used for bi-directionally transmitting clock signal and data signal respectively.