Memory system and error correcting method thereof

A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.